Search results

Alternate design for this - supporting higher clock speeds

Status: Open.

#39 In osresearch/spispy;

· Arisotura opened on Mar 6, 2025

Can't load rom into RAM

Status: Open.

#38 In osresearch/spispy;

· doob85 opened on Aug 17, 2023

quick question about hardware for this

Status: Open.

#37 In osresearch/spispy;

· hanetzer opened on Jul 16, 2023

SRAM instead ?

Status: Open.

#36 In osresearch/spispy;

· fenugrec opened on May 1, 2023

Cant build spispy because of Error in Verilog

Status: Open.

#35 In osresearch/spispy;

· doob85 opened on Nov 26, 2022

spispy on the Glasgow

Status: Open.

#34 In osresearch/spispy;

· TheWanderer1983 opened on Jun 15, 2022

Support higher SPI clock frequency

Status: Open.

#33 In osresearch/spispy;

· microxblue opened on Feb 28, 2021

Missing LICENSE

Status: Open.

#32 In osresearch/spispy;

· TechnologyClassroom opened on Nov 10, 2020

spispy CLI uses 100% CPU in monitor mode if device disconnects

Status: Open.

#28 In osresearch/spispy;

· bluecmd opened on Jan 16, 2020

Cleanup verilog directory

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

#27 In osresearch/spispy;

· osresearch opened on Jan 9, 2020

Version command should report commit hash or something useful

Status: Open.

#26 In osresearch/spispy;

· osresearch opened on Nov 30, 2019

yosys/prjrellis/nextpnr head bitstream doesn't work

Status: Open.

#25 In osresearch/spispy;

· osresearch opened on Nov 30, 2019