Remove AXI4 from Gemmini

[Ben-INL]

I am currently trying to implement Gemmini on an FPGA, but it uses too many I/Os - 363 in total, of which 268 are used solely by AXI4.
Additionally, 64 I/Os are used by the Serial TileLink interface and 31 for scalar ports.
Therefore, I am wondering: is it possible to use only the Serial TileLink interface? If so, how much would this impact performance?

[jerryz123]

On a FPGA, the AXI4 pins are intended to connect to the FPGA's MIG IP, assuming your FPGA target board has DRAM.

You can look at the Chipyard FPGA flow for some examples of boards which are integrated in this manner.