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1. Cache Cache Public

   A direct-mapped L1 cache supporting byte-, halfword-, and word-level accesses. Implements read-allocate on read miss and write-around on write miss, with proper hit/miss handling. Both design and v…

   SystemVerilog 1

2. UVM UVM Public

   SystemVerilog

3. Assertion-based-verification Assertion-based-verification Public

   SystemVerilog

4. AES-128 AES-128 Public

   SystemVerilog implementation of AES-128 encryption and decryption , designed for resource efficiency

   SystemVerilog 1